A. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor element, and more particularly to a method of manufacturing a semiconductor element such as an IC (integrated circuit), a MOS (metal oxide semiconductor) or an insulated gate bipolar transistor (hereinafter referred to as an “IGBT”).
B. Description of the Related Art
In recent years, integrated circuits (ICs) have been most commonly used in important sections in a computer or a communication device. In such ICs, a number of transistors and resistors are connected so as to form electric circuits that are integrated onto one chip. Of these ICs, those including power semiconductor elements are referred to as power ICs.
An IGBT is a power element provided with both the high speed switching and voltage driving characteristics of a MOSFET and the low on-voltage characteristic of a bipolar transistor. The IGBT has been expanding from industrial applications, which include devices such as general-purpose inverters, AC servo devices, uninterruptible power sources (UPS) and switching power sources, to consumer applications, which include devices such as microwave ranges, electric rice cookers and strobes. Development directed to next generation IGBTs also is proceeding. An IGBT having a new chip structure with an even lower on-voltage has been developed, so that devices using such IGBTs have reduced loss and enhanced efficiency.
IGBT structures may be mainly classified into punch through (PT) type, non punch through (NPT) type and field stop (FS) type. Furthermore, almost all currently mass-produced IGBTs have an n-channel type vertical double diffused structure except for those having a p-channel type structure used for audio power amplifiers. In the following the term “IGBT” refers to as an n-type IGBT, unless otherwise specified.
A PT type IGBT has a structure in which an n+-layer (n-buffer layer) is provided between a p+-epitaxial substrate and an n−-layer (n-type active layer) to allow a depletion layer in the n-type active layer to reach the n-buffer layer. This is the basic structure for main stream IGBTs. However, for an IGBT of 600V breakdown voltage series, although the n-type active layer need have a thickness only of the order of 70 μm, the total thickness including the p+-epitaxial substrate part may become as thick as of the order of 200 μm to 300 μm. This leads to development of the NPT type IGBT and the FS type IGBT. In each type, no epitaxial substrate is used. Instead, an FZ substrate is used that is formed from a crystal prepared by the FZ (Floating Zone) method to form therein a shallow p+-collector layer doped with a low dose for being thinned and provided at reduced cost.
FIG. 34 is a view showing an example of a cross sectional structure of an NPT type IGBT. NPT type IGBT 100 shown in FIG. 34 has a structure in which n−-type FZ (FZ-N) substrate 101 has gate electrode 103 of a material such as polysilicon formed on the top surface and gate oxide film 102 of a material such as SiO2 provided between the substrate and the gate electrode. In this structure, top surface electrode 105 of an aluminum silicon film, for example, is further formed on gate electrode 103 with interlayer insulator film 104 of a material such as BPSG (borophosphosilicate glass) provided between the top surface electrode and the gate electrode. On the top surface side of FZ-N substrate 101, p+-base layer 106 and n+-emitter layer 107 in p+-base layer 106 are formed. On the bottom surface side of FZ-N substrate 101 is formed p+-collector layer 108 on which bottom surface electrode 109 is formed by laminating several kinds of metal films.
In NPT type IGBT 100 with such a structure, for the p+-collector layer 108, a shallow low-level injection p+-collector is used which is doped with a low dose. In NPT type IGBT 100, no epitaxial substrate is used to make the total thickness thereof significantly less as compared with that of the above-described PT type IGBT.
In the NPT structure, hole injection rate can be controlled to enable high-speed switching without performing lifetime control of holes. The value of an on-voltage, being dependent on a thickness and specific resistance of an n-type active layer, becomes a little higher. The use of the FZ substrate instead of the above-described p+-epitaxial substrate allows a chip with the NPT structure to be produced at reduced cost.
FIG. 35 is a view showing an example of a cross sectional structure of an FS type IGBT. In FIG. 35, the same constituents as those shown in FIG. 34 are denoted by the same reference numerals and signs with detailed explanations thereof omitted.
For FS type IGBT 200 shown in FIG. 35, as for the above-described NPT type IGBT, FZ-N substrate 101 is used instead of the above-described p+-epitaxial substrate, with the total thickness thereof becoming on the order of 100 μm to 200 μm. As in the PT type IGBT, the n-type active layer is made to have a thickness on the order of 70 μm according to a breakdown voltage and is made depleted. For this purpose, in FS type IGBT 200, on the bottom surface of FZ-N substrate 101, an n+-layer (n-buffer layer) 201 is formed, on which p+-collector layer 108 and bottom surface electrode 109 are formed. In FS type IGBT 200, as in the above-described IGBT 100, lifetime control is unnecessary.
In order to lower on-voltage, a type of IGBT is used in which an IGBT with a trench structure, having a narrow and deep trench formed on the top surface of the IGBT together with a MOS gate formed on the side wall of the trench, is combined with an IGBT of an FS structure. Recently, total thickness reduction by design optimization also has been carried out.
Using the FS type IGBT 200 shown in the above-described FIG. 35 as an example, one example of a method of forming an IGBT will be explained with reference to FIG. 35 to FIG. 40. FIG. 36 is a cross sectional view taken after a top surface side process has been completed. FIG. 37 is a cross sectional view showing a substrate grinding process. FIG. 38 is a cross sectional view showing a bottom surface side ion implantation process. FIG. 39 is a cross sectional view showing a bottom surface annealing process. FIG. 40 is a cross sectional view showing a top surface electrode film forming process. In FIG. 36 to FIG. 40, the same constituents as those shown in FIG. 34 and FIG. 35 are denoted by the same reference numerals and signs with detailed explanations thereof omitted.
The processes of forming FS type IGBT 200 may be roughly classified into a top surface side process and a bottom surface side process. First, an explanation will be made about the top surface side process with reference to FIG. 36.
In the top surface side process, SiO2 and polysilicon are first deposited in this order on the top surface side of FZ-N substrate 101. The deposited SiO2 and polysilicon are then processed to form a window that penetrates gate oxide film 102 and gate electrode 103, respectively. Following this, BPSG is deposited on the surface thereof. The deposited BPSG is then processed to form a window into interlayer insulator film 104. This makes an insulated gate structure formed on the top surface side of FZ-N substrate 101.
Next, p+-base layer 106 is formed on the top surface side of the FZ-N substrate 101 and n+-emitter layer 107 is also formed. Furthermore, an aluminum silicon film is deposited so that it is in contact with n+-emitter layer 107. This layer is top surface electrode 105 that is to become the emitter electrode. The aluminum silicon film is thereafter heat-treated at a low temperature on the order of 400° C. to 500° C. to realize an interconnection with stable compatibility and low resistance.
Although its illustration was omitted in FIG. 35 and FIG. 36, an insulator protective film is formed on the top surface electrode 105 using a material such as polyimide so as to cover the surface of electrode 105.
Next, an explanation will be made about the bottom surface side process with reference to FIG. 37 to FIG. 40. In the bottom surface side process, as shown in FIG. 37, FZ-N substrate 101 is first thinned from the bottom surface to a desired thickness by carrying out back grinding or etching to produce a thinned wafer.
Next, as shown in FIG. 38, phosphorus ions (P+) and boron ions (B+) are implanted in this order onto the bottom surface side of FZ-N substrate 101 to form n+-layer 201a and p+-layer 108a, which are thereafter heat-treated (annealed) at a low temperature of 350° C. to 500° C. in an electric furnace. This activates phosphorus-implanted n+-layer 201a and boron-implanted p+-layer 108a to form n+-buffer layer 201 and p+-collector layer 108, respectively, on the bottom surface side of FZ-N substrate 101, as shown in FIG. 39.
Thereafter, as shown in FIG. 40, bottom surface electrode 109 is formed on the surface of p+-collector layer 108. It is made up of a combination of metal layers such as an aluminum layer, a titanium layer, a nickel layer and a gold layer.
Finally, the wafer is subjected to dicing into chip-like pieces. Then, in each of the chip-like pieces, aluminum wire electrodes are fixed by means of an ultrasonic wire bonder onto the surface of top surface electrode 105. Bottom surface electrode 109 is connected to a specified fixing piece with a solder layer provided between.
In recent years, a matrix converter that carries out direct AC to AC conversion without intervention of a direct current has been spotlighted. Unlike previous inverters, the matrix converter requires no capacitor to reduce supply harmonics. However, an alternating current input requires a semiconductor switch to have a high reverse breakdown voltage. Thus, use of an IGBT of this previous type needed a reverse-blocking diode connected in series thereto.
FIG. 41 is a view showing an example of a cross sectional structure of a reverse-blocking IGBT. In FIG. 41, the same constituents as those shown in FIG. 34 are denoted by the same reference numerals and signs with detailed explanations thereof omitted.
As shown in FIG. 41, reverse-blocking IGBT 300 is an IGBT which has the basic performance following that of the previous type with p+-isolation layer 301 further formed so as to provide a high reverse breakdown voltage. For reverse-blocking IGBT 300 having such a structure, no diode connected in series is necessary to allow conduction loss to be reduced by half. This largely contributes to enhancement of the conversion efficiency of the matrix converter. The technology of forming a deep junction with a depth of 100 μm or more and the technology of producing a very thin wafer with a thickness of 100 μm or less are combined to enable manufacture of a high performance reverse-blocking IGBT.
In manufacturing such an IGBT, however, there are many technical aspects of the manufacturing process that must be addressed in order to realize a thin IGBT with a thickness of the order of 70 μm. These include elimination of warping of the wafer that is caused by necessary processes such as bottom surface grinding, ion implantation to the bottom surface and bottom surface heat-treatment.
One of the technical aspects of the manufacturing processes is the technique of activating a p-type doped layer (p-layer) or an n-type doped layer (n-layer), which is necessary in order to form various kinds of semiconductor elements including the IGBTs shown here as examples. Various methods have been tried previously for this activation. Besides the method of using an electric furnace as described above, activation of a doped layer has been carried out by annealing using a laser. In this technique, a wafer is secured on a supporting substrate by an adhesive sheet to prevent cracking of the wafer and the wafer is irradiated with a laser beam to activate the p-layer and the n-layer. Activation may be carried out using the third harmonic of YAG (Yttrium Aluminum Garnet) laser (YAG3ω laser), and so forth (see, for example, JP-A-2003-59856 (Paragraph Nos. 0014 to 0025, FIG. 6 and FIG. 7).
Such laser annealing was formerly carried out by irradiating a wafer with a single pulse laser beam at a fixed period for each irradiation area and some laser irradiation devices and some laser annealing methods for the annealing are proposed (see, for example, JP-A-2001-185504 (Paragraph Nos. 0009 to 0014, FIG. 1 and FIG. 2); JP-A-2003-109912 (Paragraph Nos. 0033 to 0034, FIG. 2 and FIG. 3); JP-A-10-275781 (Paragraph Nos. 0014 to 0018, FIG. 2 and FIG. 3); JP-A-5-62924 (Paragraph Nos. 0012 to 0016, FIG. 1 and FIG. 2); JP-A-2001-156018 (Paragraph Nos. 0040 to 0076, FIG. 4 and FIG. 5); and JP-A-2000-349042 (Paragraph Nos. 0026, 0027 and 0034, FIG. 2, FIG. 3 and FIG. 4)). In these methods, attempts are made to adjust the period of the single pulse using a plurality of laser oscillators for laser beam sources to synthesize laser beams lasing in the respective laser oscillators (JP-A-2001-185504 is and JP-A-2003-109912), to adjust a pulse width (half-width) of a pulsed beam having a plurality of peaks (JP-A-10-275781), to increase an area of an irradiated region by carrying out simultaneous irradiation with laser beams to the same region (JP-A-5-62924), to make the distribution of the irradiation energy of a YAG laser beam uniform (JP-A-2001-156018), and to reflect back a laser beam reflected from a laser irradiation specimen by a mirror to irradiate the irradiation specimen again with the reflected back laser beam (JP-A-2000-349042).
In activating the p-layer and the n-layer, the p-layer cannot be made highly activated in the case of previous electric furnace annealing. Furthermore, in the method of using an adhesive sheet for preventing cracking of wafer, the permissible temperature of the adhesive sheet being usually 200° C. or less makes the use of the sheet impossible when the electric furnace annealing needs to be performed at 300° C. or more.
Moreover, when the p-layer and the n-layer are to be activated by laser annealing instead of electric furnace annealing, irradiation with a short single pulsed laser beam with a half-width of 100 ns or less such as a pulsed beam of an excimer laser can activate only to a shallow region from the surface. For example, in pn-successive layers on the bottom surface side of an FS type IGBT where the p-layer and the n-layer are successively provided from the bottom surface in that order, sufficient activation up to the n-layer is impossible. When irradiation is carried out with a beam of an all solid-state laser such as the YAG3ω laser used in a form of a single pulse, the irradiation, being carried out with a beam spot with a diameter of the order of 0.9 mm, for example, necessitates a long irradiation time. Thus, processing time for one wafer can be several hours. For example, annealing of a five-inch wafer takes on the order of two hours. Moreover, when one irradiation area is irradiated with a laser beam in which irradiation energy has been increased, traces of work damage by the laser irradiation sometime remain on the surface of the wafer.
A laser irradiation device carrying out irradiation with a laser beam having a wavelength in the range of 300 nm to 600 nm can activate a substrate, having impurity ions implanted therein, to a deep region without making the laser beam pass through the substrate. It is, however, not easy to newly make up a laser irradiation device that can carry out irradiation with the above laser beam in a pulse having a full-width at half maximum as long as 100 ns or more.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.